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Espressif Systems /ESP32-P4 /LP_AON_CLKRST /LP_AONCLKRST_HP_USB_CLKRST_CTRL0

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Interpret as LP_AONCLKRST_HP_USB_CLKRST_CTRL0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LP_AONCLKRST_USB_OTG20_SLEEP_MODE)LP_AONCLKRST_USB_OTG20_SLEEP_MODE 0 (LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN)LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN 0 (LP_AONCLKRST_USB_OTG11_SLEEP_MODE)LP_AONCLKRST_USB_OTG11_SLEEP_MODE 0 (LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN)LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN 0 (LP_AONCLKRST_USB_OTG11_48M_CLK_EN)LP_AONCLKRST_USB_OTG11_48M_CLK_EN 0 (LP_AONCLKRST_USB_DEVICE_48M_CLK_EN)LP_AONCLKRST_USB_DEVICE_48M_CLK_EN 0LP_AONCLKRST_USB_48M_DIV_NUM 0LP_AONCLKRST_USB_25M_DIV_NUM 0LP_AONCLKRST_USB_12M_DIV_NUM

Description

HP USB Clock Reset Control Register.

Fields

LP_AONCLKRST_USB_OTG20_SLEEP_MODE

unused.
LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN

unused.
LP_AONCLKRST_USB_OTG11_SLEEP_MODE

unused.
LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN

unused.
LP_AONCLKRST_USB_OTG11_48M_CLK_EN

usb otg11 fs phy clock enable.
LP_AONCLKRST_USB_DEVICE_48M_CLK_EN

usb device fs phy clock enable.
LP_AONCLKRST_USB_48M_DIV_NUM

usb 480m to 25m divide number.
LP_AONCLKRST_USB_25M_DIV_NUM

usb 500m to 25m divide number.
LP_AONCLKRST_USB_12M_DIV_NUM

usb 480m to 12m divide number.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data